Structured Computer Organization, by Tanenbaum
Chapter 3, part 2: Clocks, Memory - Latches, Registers, CPU Chips and Buses

• In many digital circuits, the order in which events happen is critical.
  
  
• Clocks are used to provide syncronization
  
  
• A clock: a circuit that emits a series of pulses with a precise
  pulse width and precise interval between consecutive pulses.
  
  
• Clock cycle time: the time interval between the corresponding edges of
  two consecutive pulses.
  
  
• Pulse frequencies are commonly between 1 and 500 MHz, corresponding to
  clock cycles of 1000 nsec to 2 nsec
  
  
• Many events may happen during a single clock cycle.
  • The clock cycle must be divided into subcycles
  • "Tap" the primary clock line and insert a circuit with a known delay in it.
  • This generates a secondary clock signal that is phase shifted from the
    primary.
• Fig. 3-21b: four time references for discrete events:
  1. Rising edge of C1
  2. Falling edge of C1
  3. Rising edge of C2
  4. Falling edge of C2
  
  
• By tying different events to the various edges, the required sequencing
  can be achieved.
  
  
• Memory - an essential component of every computer is its memory. Without
  memory there could be no computers as we know them.
  
  
• Memory is used for storing both instructions to be executed and data.
  
  
• Latch: a 1 bit memory
  
  
• Fig. 3-22a: a latch circuit built from two NOR gates.
  • This latch is called an SR latch
• SR latch: has two inputs, S, for setting the latch, and R for resetting
  The SR latch has two outputs, Q and ~Q, which are complementary.
  
  
• Unlike a combinational circuit, the outputs of the latch are not uniquely
  determined by the current inputs.
  
  
• For R=S=0, the SR latch has two stable states, 0 (Q = 0) and 1 (Q=1)
  1. Case 1, Q = 0, Fig. 3-22a. S=0, R=0, ~Q = 1. ~Q feeds the input of
     the lower NOR gate, along with R=0. The lower NOR gate outputs 0, the
     upper NOR gate outputs 1.
  2. Case 2, Q = 1, Fig. 3-22b. S=0, R=0, ~Q = 0. ~Q feeds the input of
     the lower NOR gate, along with R=0. The lower NOR gate outputs 1, the
     upper NOR gate outputs 0.
• Now examine the effect of the inputs on the state of the SR latch.
  
  
• Suppose S becomes 1 while Q = 0.
  • The inputs to the upper NOR gate are 1 and 0, the output, ~Q, becomes 0
  • This output 0 from the upper NOR gate feeds into the lower NOR gate.
  • The inputs to the lower NOR gate are 0 and 0, the output, Q, becomes 1.
  • Setting S to 1 has the effect of switching the state of the SR latch
    from 0 (Q = 0) to 1 (Q = 1)
  • Setting R to 1 when the state is 0 has no effect because the output
    of the lower NOR gate is 0 for both inputs of 10 and 11.
  
  
• Suppose R becomes 1 while Q = 1 (state = 1)
  • The output of the lower NOR gate becomes 0 (Q = 0)
  • The inputs of the upper NOR gate are now 00, and the output becomes 1
  • The state has changed from 1 to 0
  
  
• Changing the state of the SR latch:
  1. Setting S to 1: the latch will end up in state 1 (Q=1)
  2. Setting R to 1: the latch will end up in state 0 (Q=0)
  3. The SR latch circuit "remembers" whether S or R was last on
  4. If the SR latch is in state 0, R ("Reset") was last on
  5. If the SR latch is in state 1, S ("Set") was last on
  
  
• Summary table:
  1. State 0, ~Q=1, Q=0
     • S = 1, R = 0 (set)
       This changes or sets the SR latch to State 1, ~Q=0, Q=1
     • S = 0, R = 1 (reset)
       No effect on State 0, the SR latch remains in State 0, ~Q=1, Q=0
  2. State 1, ~Q=0, Q=1
     • S = 1, R = 0 (set)
       No effect on State 1, the SR latch remains in State 1, ~Q=0, Q=1
     • S = 0, R = 1 (reset)
       This resets the SR latch back to State 0, ~Q=1, Q=0
  
  
• "Set" - S=1, R=0 - means put the SR latch in State 1
  "Reset" - S=0, R=1 - means put the SR in State 0
  
  
• The state in which S=1 and R=1 is a nondeterministic state.
  • If either input returns to 0, the SR latch returns to one of the
    two states
  • If both S and R return to 0 at the same time, the latch goes to
    one of the two stable states (can't determine which one, could be
    either)
  
  
• Clocked SR latches