The MIC-1 Architecture

The MIC-1 is a hypothetical computer defined in the book by Andrew S. Tannenbaum, Structured Computer Organization, 3rd Edition. It is used to help teach the how modern computers are designed at the Microprogramming level. The materials below may help in your understanding of this machine, and how to write a simulation of its behavior.

The Basic MIC-1

The Registers

There are 16 registers in the MIC-1. The hardware refers to them numerically, but the following acronyms are used to better understand their use.

Number	Acronym and Meaning	Use
0	PC or Program Counter	Keeps track of user's instruction position in the program
1	AC or Accumulator	Holds the current numerical total from the ALU.
2	SP or Stack Pointer	Holds return addresses for subroutine calls
3	IR or Instruction Register	Hold the current instruction
4	TIR or Temporary Instruction Register	Temporary values as instruction is decoded
5	0 Value or Zero Register	Hard wired zero that can be used for clearing other values
6	+1 or Plus One Register	Hard wired plus one for incrementing quickly
7	-1 or Minus One Register	Hard wired minus one for decrementing quickly
8	Amask or Address Mask	Pattern of ones and zeros that can be used to AND with instruction to isolate just the Address.
9	Smask or Stack Mask	Pattern of ones and zeros that can be used to AND with instruction to isolate the Stack Offset
10 to 15	A through F Registers	General purpose registers that can be used to store temporary values

Other Components

Acronym	Description and Use
A-Latch	Holds values sent out over the A-Bus that could then be sent AMUX which will then decide if it should be sent to the left side of the ALU or discarded.
B-Latch	Holds values sent out over the B-Bus that could then be either sent to the right side of the ALU, or to the MBR , or both.
AMUX	The A-Multiplexer selects one of two inputs to send to the left sine of the ALU.
ALU	The Arithmetic Logic Unit can select among four possible functions, and then sends the result on to the Shifter.
Shifter	The Shifter will select among various shift operations and then sends the value out on the C-Bus which also sends a copy to the MBR which may or may not use it.
MAR	The Memory Address Register holds the address of some place in Main Memory. This register can only be loaded from the data from the B-Latch (B-Bus).
MBR	The Memory Buffer Register will read or write its contents to Main Memory depending upon its control lines. The address that it uses for either of these operations is held in the MAR. The MBR can also be filled from the C-Bus.
Main Memory	The Main Memory of the MIC-1 is a sequential array of 16-bit words that can hold a user's program. In the example shown here, the lowest memory address is 0000 and the highest is 9999, but the actual highest address would be controlled by the value in Register 8 ( A-Mask ).

The Micro-Instruction

Synchronization of the various parts of the MIC-1 are controlled by a separate Control Store of 32-bit Micro-instructions. These instructions cannot be accessed by the user, but control the action of of the basic commands of the MIC-1. The following fields are activated according to the bit pattern in the micro-instruction and cause the resulting action.

Field	Numerical Value and Action
AMUX	A-Multiplexer 0 - Load the ALU from the A-Latch 1 - Load the ALU from the MBR
COND	Conditional Branch 0 - No Branch 1 - Branch to value in ADDR if ALU is Negative 2 - Branch to value in ADDR if ALU is Zero 3 - Branch to value in ADDR Always
ALU	Arithemtic Logic Unit Operations 0 - A + B (ADD from A-Latch Side and B-Latch) 1 - A & B (AND from A-Latch Side and B-Latch) 2 - A (Just let A-latch side pass through and do nothing) 3 - !A (INVERT A)
SH	Shifter Operations 0 - NO Shift 1 - Shift RIGHT one bit 2 - Shift LEFT one bit 3 - Not Used
MBR	Memory Buffer Register 0 - Do Not Load the Memory Buffer Register 1 - Load the Memory Buffer Register from the C-Bus
MAR	Memory Address Register 0 - Do Not Load the Memory Address Register 1 - Load the Memory Addres Register from the B-Latch
RD	Read from Main Memory 0 - Do Not Read from Memory 1 - Read into MBR, the contents of Main Memory according to the Address in MAR
WR	Write to Main Memory 0 - Do Not Write to Memory 1 - Write contents of MBR to Main Memory according to the Address in MAR
ENC	Enable the C-Bus 0 - Do Not Activate the C-Bus (no storing of Values into any of the 16 Registers 1 - Activate C-Bus, or store the value leaving the Shifter into the register specified in the C-Field
C	C-Bus Select Register 0 - 15 - Which of 16 Registers will be stored from the C-Bus. ENC must be active, too.
B	B-Bus Select Register 0 - 15 - Select one of 16 Registers to be loaded onto the B-Bus and B-Latch
A	A-Bus Select Register 0 - 15 - Select one of 16 Registers to be loaded onto the A-Bus and A-Latch
ADDR	Address Field 0 - 255 - One of 256 Addresses (Micro-instructions) in the Control Store. Will be used by the COND field for Microcode jumps.

Example Micro-Instructions and Their Meaning

Instruction - 0 00 10 00 0110 0 0000 0000 0000 00000000
Meaning - mar := pc; rd;

Instruction - 1 00 10 00 0000 1 0011 0000 0000 00000000
Meaning - ir := mbr;

Instruction - 0 01 10 10 0110 1 1000 0000 0000 00011001
Meaning - tir := lshift(tir); if N then goto 25;

Mic-1 Assembly Language

0000xxxxxxxxxxxx LODD Load Direct
0001xxxxxxxxxxxx STOD Store Direct
0010xxxxxxxxxxxx ADDD Add Direct
0011xxxxxxxxxxxx SUBD Subtract Direct
0100xxxxxxxxxxxx JPOS Jump Positive
0101xxxxxxxxxxxx JZER Jump Zero
0110xxxxxxxxxxxx JUMP Jump
0111xxxxxxxxxxxx LOCO Load Constant
1000xxxxxxxxxxxx LODL Load Local
1001xxxxxxxxxxxx STOL Store Local
1010xxxxxxxxxxxx ADDL Add Local
1011xxxxxxxxxxxx SUBL Subtract Local
1100xxxxxxxxxxxx JNEG Jump Negative
1101xxxxxxxxxxxx JNZE Jump Not Zero
1110xxxxxxxxxxxx CALL Call Subroutine
1111000000000000 PSHI Push Indirect
1111001000000000 POPI Pop Indirect
1111010000000000 PUSH Push
1111011000000000 POP Pop
1111100000000000 RETN Return from Subr.
1111101000000000 SWAP Swap
11111100yyyyyyyy INSP Increment Stack Ptr.
11111110yyyyyyyy DESP Decrement Stack Ptr.